Hardware manual

Rev. 3.0, 09/98, page 340 of 361
P9DRPort 9 Data Register H'FFC1 Port 9
Bit
Initial value
Read/Write
Notes: * Depends on the level of pin P9
6 .
7
P9
6
0
R/W
6
P9
6
*
R
5
P9
5
0
R/W
4
P9
4
0
R/W
3
P9
3
0
R/W
0
P9
0
0
R/W
2
P9
2
0
R/W
1
P9
1
0
R/W
STCRSerial/Timer Control Register H'FFC3 TMR0/1
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
0
ICKS0
0
R/W
2
MPE
0
R/W
1
ICKS1
0
R/W
Multiprocessor Enable
Multiprocessor communication function is disabled.
Multiprocessor communication function is enabled.
0
1
Internal Clock Source Select
See TCR under TMR0 and TMR1.