Hardware manual

Rev. 3.0, 09/98, page 338 of 361
P5DRPort 5 Data Register H'FFBA Port 5
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
0
P5
0
0
R/W
2
P5
2
0
R/W
1
P5
1
0
R/W
P6DDRPort 6 Data Direction Register H'FFB9 Port 6
Bit
Initial value
Read/Write
7
P6
7 DDR
0
W
6
P6
6 DDR
0
W
5
P6
5 DDR
0
W
4
P6
4 DDR
0
W
3
P6
3 DDR
0
W
0
P6
0 DDR
0
W
2
P6
2 DDR
0
W
1
P6
1 DDR
0
W
Port 6 Input/Output Control
Input port
Output port
0
1
P6DRPort 6 Data Register H'FFBB Port 6
Bit
Initial value
Read/Write
7
P6
7
0
R/W
6
P6
6
0
R/W
5
P6
5
0
R/W
4
P6
4
0
R/W
3
P6
3
0
R/W
0
P6
0
0
R/W
2
P6
2
0
R/W
1
P6
1
0
R/W
P7DRPort 7 Data Register H'FFBE Port 7
Bit
Initial value
Read/Write
Note: * Depends on the levels of pins P7
7 to P7 0 .
7
P7
7
*
R
6
P7
6
*
R
5
P7
5
*
R
4
P7
4
*
R
3
P7
3
*
R
0
P7
0
*
R
2
P7
2
*
R
1
P7
1
*
R