Hardware manual

Rev. 3.0, 09/98, page 330 of 361
TCRTimer Control Register H'FFA0 PWM0
Bit
Initial value
Read/Write
7
OE
0
R/W
6
OS
0
R/W
5
—
1
—
4
—
1
—
3
—
1
—
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
Clock Select (Values When Ø= 10 MHz)
Ø/2 200ns 50µs 20kHz
Ø/8 800ns 200µs 5kHz
Ø/32 3.2µs 800µs 1.25kHz
Ø/128 12.8µs 3.2ms 312.5Hz
Ø/256 25.6µs 6.4ms 156.3Hz
Ø/1024 102.4µs 25.6ms 39.1Hz
Ø/2048 204.8µs 51.2ms 19.5Hz
Ø/4096 409.6µs 102.4ms 9.8Hz
Internal
clock Freq.
Reso-
lution
PWM
period
PWM
frequency
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Output Select
0 Positive logic
Negative logic
1
Output Enable
0 PWM output disabled; TCNT cleared to H'00 and stops.
PWM output enabled; TCNT runs.
1
DTRDuty Register H'FFA1 PWM0
Bit
Initial value
Read/Write
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
Pulse duty cycle