Hardware manual

Rev. 3.0, 09/98, page 327 of 361
TCRTimer Control Register H'FF96 FRT
Bit
Initial value
Read/Write
7
IEDGA
0
R/W
6
IEDGB
0
R/W
5
IEDGC
0
R/W
4
IEDGD
0
R/W
3
BUFEA
0
R/W
0
CKS0
0
R/W
2
BUFEB
0
R/W
1
CKS1
0
R/W
Clock enable 0
0 0 Internal clock source: Ø/2
1 Internal clock source: Ø/8
0 Internal clock source: Ø/32
1 External clock source: counted on rising edge
1
1
1
Buffer Enable B
0 ICRD is used for input capture D.
ICRD is buffer register for input capture B.
1
Input Edge Select D
0 Falling edge of FTID is valid.
Rising edge of FTID is valid.
1
Buffer Enable A
0 ICRC is used for input capture C.
ICRC is buffer register for input capture A.
1
Input Edge Select C
0 Falling edge of FTIC is valid.
Rising edge of FTIC is valid.
1
Input Edge Select B
0 Falling edge of FTIB is valid.
Rising edge of FTIB is valid.
1
Input Edge Select A
0 Falling edge of FTIA is valid.
Rising edge of FTIA is valid.
1