Hardware manual

Rev. 3.0, 09/98, page 325 of 361
TCSRTimer Control/Status Register H'FF91 FRT
Bit
Initial value
Read/Write
7
ICFA
0
R/(W)
6
ICFB
0
R/(W)
5
ICFC
0
R/(W)
4
ICFD
0
R/(W)
3
OCFA
0
R/(W)
0
CCLRA
0
R/W
2
OCFB
0
R/(W)
1
OVF
0
R/(W)
*******
0 0 Cleared when CPU reads OVF = "1," then writes
"0" in OVF.
Timer Overflow
1 Set when FRC changes from H'FFFF to H'0000.
0 Cleared when CPU reads OCFB = "1", then writes
"0" in OCFB.
1 Set when FRC = OCRB.
0 Cleared when CPU reads OCFA = "1", then writes
"0" in OCFA.
1 Set when FRC = OCRA.
0 Cleared when CPU reads ICFD = "1", then writes
"0" in ICFD.
1 Set by FTID input.
0 Cleared when CPU reads ICFC = "1", then writes
"0" in ICFC.
1 Set by FTID input.
0 0 Cleared when CPU reads ICFB = "1", then writes
"0" in ICFB.
1 Set when FTIB input causes FRC to be copied to ICRB.
0 Cleared when CPU reads ICFA = "1", then writes
"0" in ICFA.
1 Set when FTIA input causes FRC to be copied to ICRA.
0 FRC count is not cleared.
FRC count is cleared by compare-match A.
Counter Clear A
1
Output Compare Flag B
Output Compare Flag A
Input Capture Flag D
Input Capture Flag C
Input Capture Flag B
Input Capture Flag A
Note: * Software can write a "0" in bits 7 to 1 to clear the flags, but cannot
write a "1" in these bits.