Hardware manual

Rev. 3.0, 09/98, page 322 of 361
SSRSerial Status Register H'FF8C SCI1
Bit
Initial value
Read/Write
Note: * Software can write a “0” in bits 7 to 3 to clear the flags, but cannot write a “1” in these bits.
7
TDRE
1
R/(W)
6
RDRF
0
R/(W)
5
ORER
0
R/(W)
0
MPBT
0
R/W
2
TEND
1
R
1
MPB
0
R
4
FER
0
R/(W)
Receive Data Register Full
0
Cleared when CPU reads RDRF = “1,” then writes “0” in RDRF.
1
Set when one character is received normally and transferred from RSR to RDR.
Transmit Data Register Empty
0
Cleared when CPU reads TDRE = “1,” then writes “0” in TDRE.
1 Set when:
1. Data is transferred from TDR to TSR.
2. TE is cleared while TDRE = “0.”
Transmit End
0
Cleared when CPU reads TDRE = “1,” then writes “0” in TDRE.
1
Set to “1” when TE = “0,” or when TDRE = “1” at the end of character transmission.
Parity Error
0
Cleared when CPU reads PER = “1,” then writes “0” in PER.
1
Set when a parity error occurs (parity of receive data does not match parity selected by O/E bit in SMR).
Framing Error
0
Cleared when CPU reads FER = “1,” then writes “0” in FER.
1
Set when a framing error occurs (stop bit is “0”).
Overrun Error
0
Cleared when CPU reads ORER = “1,” then writes “0” in ORER.
1 Set when an overrun error occurs (next data is completely received while
RDRF bit is set to “1”).
Multiprocessor Bit
Multiprocessor Bit transfer
0
Multiprocessor bit = “0” in receive data.
1 Multiprocessor bit = “1” in receive data.
0 Multiprocessor bit = “0” in transmit data.
1 Multiprocessor bit = “1” in transmit data.
3
PER
0
R/(W)
*****