Hardware manual

Rev. 3.0, 09/98, page 315 of 361
Bit Names
Addr.
(last
byte)
Register
Name
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
H'C0 P9DDR P9
7
DDR P9
6
DDR P9
5
DDR P9
4
DDR P9
3
DDR P9
2
DDR P9
1
DDR P9
0
DDR Port 9
H'C1 P9DR P9
7
P9
6
P9
5
P9
4
P9
3
P9
2
P9
1
P9
0
H'C2
 
H'C3 STCR

MPE ICKS1 ICKS0
H'C4 SYSCR SSBY STS2 STS1 STS0

NMIEG DPME RAME
H'C5 MDCR

MDS1 MDS0
H'C6 ISCR IRQ
7
SC IRQ
6
SC IRQ
5
SC IRQ
4
SC IRQ
3
SC IRQ
2
SC IRQ
1
SC IRQ
0
SC
H'C7 IER IRQ
7
EIRQ
6
EIRQ
5
EIRQ
4
EIRQ
3
EIRQ
2
EIRQ
1
EIRQ
0
E
System
control
H'C8 TCR CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 TMR0
H'C9 TCSR CMFB CMFA OVF

OS3 OS2 OS1 OS0
H'CA TCORA
H'CB TCORB
H'CC TCNT
H'CD
 
H'CE
 
H'CF
 
H'D0 TCR CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 TMR1
H'D1 TCSR CMFB CMFA OVF

OS3 OS2 OS1 OS0
H'D2 TCORA
H'D3 TCORB
H'D4 TCNT
H'D5
 
H'D6
 
H'D7
 
H'D8 SMR C/
A
CHR PE O/
E
STOP MP CKS1 CKS0 SCI0
H'D9 BRR
H'DA SCR TIE RIE TE RE MPIE TEIE CKE1 CKE0
H'DB TDR
H'DC SSR TDRE RDRF ORER FER PER TEND MPB MPBT
H'DD RDR
H'DE
 
H'DF
 
Notes: TMR0: 8-Bit Timer channel 0
TMR1: 8-Bit Timer channel 1
SCI0: Serial Communication Interface 0