Hardware manual

Rev. 3.0, 09/98, page 312 of 361
Table A.4 Number of Cycles in Each Instruction (cont)
Instruction Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
SHAL SHAL.B Rd 1
SHAR SHAR.B Rd 1
SHLL SHLL.B Rd 1
SHLR SHLR.B Rd 1
SLEEP SLEEP 1
STC STC CCR, Rd 1
SUB SUB.B Rs, Rd
SUB.W Rs, Rd
1
1
SUBS SUBS.W #1/2, Rd 1
SUBX SUBX.B #xx:8, Rd
SUBX.B Rs, Rd
1
1
XOR XOR.B #xx:8, Rd
XOR.B Rs, Rd
1
1
XORC XORC #xx:8, CCR 1
Note: All values left blank are zero.