Hardware manual

Rev. 3.0, 09/98, page 310 of 361
Table A.4 Number of Cycles in Each Instruction (cont)
Instruction Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
BSR BSR d:8 2 1
BST BST #xx:3, Rd
BST #xx:3, @Rd
BST #xx:3, @aa:8
1
2
2
2
2
BTST BTST #xx:3, Rd
BTST #xx:3, @Rd
BTST #xx:3, @aa:8
BTST Rn, Rd
BTST Rn, @Rd
BTST Rn, @aa:8
1
2
2
1
2
2
1
1
1
1
BXOR BXOR #xx:3, Rd
BXOR #xx:3, @Rd
BXOR #xx:3, @aa:8
1
2
2
1
1
CMP CMP.B #xx:8, Rd
CMP.B Rs, Rd
CMP.W Rs, Rd
1
1
1
DAA DAA.B Rd 1
DAS DAS.B Rd 1
DEC DEC.B Rd 1
DIVXU DIVXU.B Rs, Rd 1 12
EEPMOV EEPMOV 2 2n+2
*
1
INC INC.B Rd 1
JMP JMP @Rn
JMP @aa:16
JMP @@aa:8
2
2
21
2
2
JSR JSR @Rn
JSR @aa:16
JSR @@aa:8
2
2
21
1
1
1
2
LDC LDC #xx:8, CCR
LDC Rs, CCR
1
1
MOV MOV.B #xx:8, Rd
MOV.B Rs, Rd
MOV.B @Rs, Rd
MOV.B @(d:16,Rs),
Rd
1
1
1
2
1
1
Notes: All values left blank are zero.
*
n: Initial value in R4L. Source and destination are accessed n + 1 times each.