Hardware manual

Rev. 3.0, 09/98, page 20 of 361

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The @−Rn mode is used with MOV instructions that store register contents to memory.

It is similar to the register indirect mode, but the 16-bit general register specified in the register

field of the instruction is decremented before the operand is accessed. The size of the

decrement is 1 or 2 depending on the size of the operand: 1 for MOV.B; 2 for MOV.W. For

MOV.W, the original contents of the 16-bit general register must be even.

(5) Absolute Address@aa:8 or @aa:16: The instruction specifies the absolute address of the

operand in memory. The MOV.B instruction uses an 8-bit absolute address of the form H'FFxx.

The upper 8 bits are assumed to be 1, so the possible address range is H'FF00 to H'FFFF (65280 to

65535). The MOV.B, MOV.W, JMP, and JSR instructions can use 16-bit absolute addresses.

(6) Immediate#xx:8 or #xx:16: The instruction contains an 8-bit operand in its second byte,

or a 16-bit operand in its third and fourth bytes. Only MOV.W instructions can contain 16-bit

immediate values.

The ADDS and SUBS instructions implicitly contain the value 1 or 2 as immediate data. Some bit

manipulation instructions contain 3-bit immediate data (#xx:3) in the second or fourth byte of the

instruction, specifying a bit number.

(7) Program-Counter-Relative@(d:8, PC): This mode is used to generate branch addresses

in the B

and BSR instructions. An 8-bit value in byte 2 of the instruction code is added as a

sign-extended value to the program counter contents. The result must be an even number. The

possible branching range is −126 to +128 bytes (−63 to +64 words) from the current address.

(8) Memory Indirect@@aa:8: This mode can be used by the JMP and JSR instructions. The

second byte of the instruction code specifies an 8-bit absolute address from H'0000 to H'00FF (0

to 255). The word located at this address contains the branch address. The upper 8 bits of the

absolute address are an “0” (H'00), thus the branch address is limited to values from 0 to 255

(H'0000 to H'00FF). Note that addresses H'0000 to H'0047 (0 to 71) are located in the vector

table.

If an odd address is specified as a branch destination or as the operand address of a MOV.W

instruction, the least significant bit is regarded as “0,” causing word access to be performed at the

address preceding the specified address. See section 2.4.2, “Memory Data Formats,” for further

information.