Hardware manual

Rev. 3.0, 09/98, page 297 of 361
Appendix A CPU Instruction Set
A.1 Instruction Set List
Operation Notation
Rd8/16 General register (destination) (8 or 16 bits)
Rs8/16 General register (source) (8 or 16 bits)
Rn8/16 General register (8 or 16 bits)
CCR Condition code register
N N (negative) flag in CCR
Z Z (zero) flag in CCR
V V (overflow) flag in CCR
C C (carry) flag in CCR
PC Program counter
SP Stack pointer
#xx:3/8/16 Immediate data (3, 8, or 16 bits)
d:8/16 Displacement (8 or 16 bits)
@aa:8/16 Absolute address (8 or 16 bits)
+ Addition
− Subtraction
× Multiplication
÷ Division
∧ AND logical
∨ OR logical
⊕ Exclusive OR logical
→ Move
 Not
Condition Code Notation
Modified according to the instruction result
* Undetermined (unpredictable)
0 Always cleared to “0”
 Not affected by the instruction result