Rev. 3.0, 09/98, page 289 of 361
(2) Basic Bus Cycle (with 1 Wait State) in Expanded Modes
Ø
A
15 + A0
AS, RD
D
7 to D0
(Read)
D
7 to D0
(Write)
WR
T
1
WAIT
T2 TW T3
tWTS tWTH tWTS tWTH
Figure 16.5 Basic Bus Cycle (with 1 wait state) in Expanded Modes
