Hardware manual

Rev. 3.0, 09/98, page 288 of 361
16.3.1 Bus Timing
(1) Basic Bus Cycle (without Wait States) in Expanded Modes
Ø
A
15 + A 0
AS, RD
D
7 to D 0
(Read)
D
7 to D 0
(Write)
WR
t
CH
t AD
t cr
t cyc
T 1
t CL
t cf
t ASD
t ASI
t SC
t RDH t RDS
t SD
t WSW
t WSD
t AS2 t AH
t WDS t WDD t WDH
t ACC
t AH
T 2 T 3
Figure 16.4 Basic Bus Cycle (without wait states) in Expanded Modes