Hardware manual

Rev. 3.0, 09/98, page 284 of 361
Table 16.8 Timing Conditions of On-Chip Supporting Modules
Condition A: V
CC
= 5.0V ±10%, V
SS
= 0V, φ = 0.5MHz to maximum operating frequency,
Ta = −20 to 75°C (regular specifications),
Ta = −40 to 85°C (wide-range specifications)
Condition B: V
CC
= 3.0V ±10%, V
SS
= 0V, φ = 0.5MHz to maximum operating frequency,
Ta = −20 to 75°C
Condition
B Condition A
5MHz 6MHz 8MHz 10MHz
Item Symbol Min Max Min Max Min Max Min Max Unit
Measurement
Conditions
FRT
Timer output
delay time
t
FTOD

150

100

100

100 ns Fig. 16.10
Timer input setup
time
t
FTIS
80

50

50

50

ns Fig. 16.10
Timer clock input
setup time
t
FTCS
80

50

50

50

ns Fig. 16.11
Timer clock pulse
width
t
FTCWH
t
FTCWL
1.5

1.5

1.5

1.5

tcyc Fig. 16.11
TMR Timer output
delay time
t
TMOD

150

100

100

100 ns Fig. 16.12
Timer reset input
setup time
t
TMRS
80

50

50

50

ns Fig. 16.14
Timer clock input
setup time
t
TMCS
80

50

50

50

ns Fig. 16.13
Timer clock pulse
width (single
edge)
t
TMCWH
1.5

1.5

1.5

1.5

tcyc Fig. 16.13
Timer clock pulse
width (both
edges)
t
TMCWL
2.5

2.5

2.5

2.5

tcyc Fig. 16.13
PWM
Timer output
delay time
t
PWOD

150

100

100

100 ns Fig. 16.15
(Async) t
scyc
4

4

4

4

tcyc Fig. 16.16SCI Input
clock
cycle
(Sync) t
scyc
6

6

6

6

tcyc Fig. 16.16
Transmit data
delay time (Sync)
t
TXD

200

100

100

100 ns Fig. 16.16
Receive data
setup time (Sync)
t
RXS
150

100

100

100

ns Fig. 16.16
Receive data hold
time (Sync)
t
RXH
150

100

100

100

ns Fig. 16.16
Input clock pulse
width
t
SCKW
0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tscyc Fig. 16.17