Hardware manual

Rev. 3.0, 09/98, page 268 of 361
15.3 Sleep Mode
The sleep mode provides an effective way to conserve power while the CPU is waiting for an
external interrupt or an interrupt from an on-chip supporting module.
15.3.1 Transition to Sleep Mode
When the SSBY bit in the system control register is cleared to “0,” execution of the SLEEP
instruction causes a transition from the program execution state to the sleep mode. After
executing the SLEEP instruction, the CPU halts, but the contents of its internal registers remain
unchanged. The on-chip supporting modules continue to operate normally.
15.3.2 Exit from Sleep Mode
The chip wakes up from the sleep mode when it receives an internal or external interrupt request,
or a Low input at the RES or STBY pin.
(1) Wake-Up by Interrupt: An interrupt releases the sleep mode and starts the CPU’s interrupt-
handling sequence.
If an interrupt from an on-chip supporting module is disabled by the corresponding enable/disable
bit in the module’s control register, the interrupt cannot be requested, so it cannot wake the chip
up. Similarly, the CPU cannot be awoken by an interrupt other than NMI if the I (interrupt mask)
bit in the CCR (condition code register) is set when the SLEEP instruction is executed.
(2) Wake-Up by RES pin: When the RES pin goes Low, the chip exits from the sleep mode to
the reset state.
(3) Wake-Up by STBY pin: When the STBY pin goes Low, the chip exits from the sleep mode
to the hardware standby mode.