Hardware manual

Rev. 3.0, 09/98, page 266 of 361
15.2 System Control Register: Power-Down Control Bits
Bits 7 to 4 of the system control register (SYSCR) concern the power-down state. Specifically,
they concern the software standby mode.
Table 15.2 lists the attributes of the system control register.
Table 15.2 System Control Register
Name Abbreviation R/W Initial Value Address
System control register SYSCR R/W H'09 H'FFC4
Bit:76543210
SSBY STS2 STS1 STS0  NMIEG DPME RAME
Initial value:00001001
Read/Write: R/W R/W R/W R/W  R/W R/W R/W
Bit 7Software Standby (SSBY): This bit enables or disables the transition to the software
standby mode.
On recovery from the software standby mode by an external interrupt, SSBY remains set to “1.”
To clear this bit, software must write a “0.”
Bit 7
SSBY Description
0 The SLEEP instruction causes a transition to the sleep mode. (Initial value)
1 The SLEEP instruction causes a transition to the software standby mode.
Bits 6 to 4Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the clock settling
time when the chip recovers from the software standby mode by an external interrupt. During the
selected time, the clock oscillator runs but clock pulses are not supplied to the CPU or the on-chip
supporting modules.
Bit 6
STS2
Bit 5
STS1
Bit 4
STS0 Description
0 0 0 Settling time = 8192 states (Initial value)
0 0 1 Settling time = 16384 states
0 1 0 Settling time = 32768 states
0 1 1 Settling time = 65536 states
1 Settling time = 131072 states