Hardware manual

Rev. 3.0, 09/98, page 265 of 361
Section 15 Power-Down State
15.1 Overview
The H8/338 Series has a power-down state that greatly reduces power consumption by stopping
some or all of the chip functions. The power-down state includes three modes:
(1) Sleep mode
−
a software-triggered mode in which the CPU halts but the rest of the chip
remains active
(2) Software standby mode
−
a software-triggered mode in which the entire chip is inactive
(3) Hardware standby mode
−
a hardware-triggered mode in which the entire chip is inactive
Table 15.1 lists the conditions for entering and leaving the power-down modes. It also indicates
the status of the CPU, on-chip supporting modules, etc. in each power-down mode.
Table 15.1 Power-Down State
Mode
Entering
Procedure Clock CPU
CPU
Reg’s.
Sup.
Mod. RAM I/O Ports
Exiting
Methods
Sleep
mode
Execute
SLEEP
instruction
Run Halt Held Run Held Held
• Interrupt
• RES
• STBY
Software
standby
mode
Set SSBY bit
in SYSCR to
“1,” then
execute
SLEEP
instruction
Halt Halt Held Halt and
initialized
Held Held
• NMI
• IRQ
0
− IRQ
2
• RES
• STBY
Hardware
standby
mode
Set
STBY
pin
to Low level
Halt Halt Not held Halt and
initialized
Held High
impedance
state
• STBY
High,
then
RES
Low
→
High
Notes: 1. SYSCR: System control register
2. SSBY: Software standby bit