Hardware manual
Rev. 3.0, 09/98, page 250 of 361
13.3 RAM Enable Bit (RAME) in System Control Register (SYSCR)
The on-chip RAM is enabled or disabled by the RAME (RAM Enable) bit in the system control
register (SYSCR).
Bit:76543210
SSBY STS2 STS1 STS0 NMIEG DPME RAME
Initial value:00001001
Read/Write: R/W R/W R/W R/W R/W R/W R/W
The only bit in the system control register that concerns the on-chip RAM is the RAME bit. See
section 2.2, "System Control Register," for the other bits.
Bit 0RAM Enable (RAME): This bit enables or disables the on-chip RAM.
The RAME bit is initialized to "1" on the rising edge of the RES signal, so a reset enables the on-
chip RAM. The RAME bit is not initialized in the software standby mode.
Bit 7
RAME Description
0 On-chip RAM is disabled.
1 On-chip RAM is enabled. (Initial value)
13.4 Operation
13.4.1 Expanded Modes (Modes 1 and 2)
If the RAME bit is set to "1," accesses to addresses H'F780 to H'FF7F in the H8/338 and addresses
H'FB80 to H'FF7F in the H8/337 and H8/336 are directed to the on-chip RAM. If the RAME bit
is cleared to "0," accesses to these addresses are directed to the external data bus.
13.4.2 Single-Chip Mode (Mode 3)
If the RAME bit is set to "1," accesses to addresses H'F780 to H'FF7F in the H8/338 and addresses
H'FB80 to H'FF7F in the H8/337 and H8/336 are directed to the on-chip RAM.
If the RAME bit is cleared to "0," the on-chip RAM data cannot be accessed. Attempted write
access has no effect. Attempted read access always results in H'FF data being read.