Hardware manual

Rev. 3.0, 09/98, page 241 of 361
Table 11.4 (b) A/D Conversion Time (Scan mode)
CKS = “0” CKS = “1”
Item Symbol Min Typ Max Min Typ Max
Synchronization delay t
D
18  33 10  17
Input sampling time t
SPL
 63 31 
Total A/D conversion time t
CONV
259  274 131  138
Note: Values in the tables above are numbers of states.
11.3.4 External Trigger Input Timing
A/D conversion can be started by external trigger input at the ADTRG pin. This input is enabled
or disabled by the TRGE bit in the A/D control register (ADCR). If the TRGE bit is set to “1,”
when a falling edge of ADTRG is detected the ADST bit is set to “1” and A/D conversion begins.
Subsequent operation in both single and scan modes is the same as when the ADST bit is set to
“1” by software.
Figure 11.5 shows the trigger timing.
Ø
Internal
trigger signal
ADTRG
ADST
A/D conversion
Figure 11.5 External Trigger Input Timing