Hardware manual

Rev. 3.0, 09/98, page 240 of 361
Ø
Internal
address bus
Write signal
Input sampling
timing
ADF
(2)
t
D t SPL
(1)
(1)
(2)
t
D
t SPL
t CONV
Legend:
: ADCSR write cycle
: ADCSR address
: Synchronization delay
: Input sampling time
: Total A/D conversion time
t CONV
Figure 11.4 A/D Conversion Timing
Table 11.4 (a) A/D Conversion Time (Single mode)
CKS = “0” CKS = “1”
Item Symbol Min Typ Max Min Typ Max
Synchronization delay t
D
18  33 10  17
Input sampling time t
SPL
 63 31 
Total A/D conversion time t
CONV
227  242 115  122