Hardware manual

Rev. 3.0, 09/98, page 239 of 361
11.3.3 Input Sampling Time and A/D Conversion Time
The A/D converter includes a built-in sample-and-hold circuit. Sampling of the input starts at a
time tD after the ADST bit is set to “1.” The sampling process lasts for a time t
SPL
. The actual
A/D conversion begins after sampling is completed. Figure 11.4 shows the timing of these steps.
Table 11.4 (a) lists the conversion times for the single mode. Table 11.4 (b) lists the conversion
times for the scan mode.
The total conversion time (t
CONV
) includes tD and t
SPL
. The purpose of t
D
is to synchronize the
ADCSR write time with the A/D conversion process, so the length of t
D
is variable. The total
conversion time therefore varies within the minimum to maximum ranges indicated in table 11.4
(a) and (b).
In the scan mode, the ranges given in table 11.4 (b) apply to the first conversion. The length of the
second and subsequent conversion processes is fixed at 256 states (when CKS = “0”) or 128 states
(when CKS = “1”).