Hardware manual

Rev. 3.0, 09/98, page 238 of 361
(4) After all selected channels (AN
0
to AN
2
) have been converted, the AD converter sets the ADF
bit to “1.” If the ADIE bit is set to “1,” an A/D interrupt (ADI) is requested. Then the A/D
converter begins converting AN0 again.
(5) Steps (2) to (4) are repeated cyclically as long as the ADST bit remains set to “1.”
To stop the A/D converter, software must clear the ADST bit to “0.”
Regardless of which channel is being converted when the ADST bit is cleared to “0,” when the
ADST bit is set to “1” again, conversion begins from the the first selected channel (AN
0
).
Waiting Waiting
A/D conver-
sion (4)
Waiting
Continuous A/D conversion
A/D conver-
sion (1)
A/D conversion result (2)
A/D conversion result (4)
A/D conver-
sion result (1)
A/D conversion result (3)
Transfer
Waiting
A/D conver-
sion (3)
Waiting
Waiting
Set*
Clear*1
Clear*1
ADST
ADF
Channel 0
(AN
0)
Channel 1
(AN
1)
Channel 2
(AN
2)
Channel 3
(AN
3)
ADDRA
ADDRB
ADDRC
ADDRD
Waiting
A/D conver-
sion (2)
Waiting
A/D conver-
sion (5)
Waiting
*
2
Notes: 1. indicates execution of a software instruction
2. Data undergoing conversion when ADST bit is cleared are ignored.
A/D conversion
time
Figure 11.3 A/D Operation in Scan Mode (when Channels 0 to 2 are Selected)