Hardware manual
Rev. 3.0, 09/98, page 231 of 361
Bit 7A/D End Flag (ADF): This status flag indicates the end of one cycle of A/D conversion.
Bit 7
ADF Description
0 To clear ADF, the CPU must read ADF after it has been set to “1,” (Initial value)
then write a “0” in this bit.
1 This bit is set to 1 at the following times:
(1) Single mode: when one A/D conversion is completed.
(2) Scan mode: when inputs on all selected channels have been converted.
Bit 6A/D Interrupt Enable (ADIE): This bit selects whether to request an A/D interrupt
(ADI) when A/D conversion is completed.
Bit 6
ADIE Description
0 The A/D interrupt request (ADI) is disabled. (Initial value)
1 The A/D interrupt request (ADI) is enabled.
Bit 5A/D Start (ADST): The A/D converter operates while this bit is set to “1.” This bit can
be set to “1” by the external trigger signal ADTRG.
Bit 5
ADST Description
0 A/D conversion is halted. (Initial value)
1
(1) Single mode: One A/D conversion is performed. The ADST bit is automatically
cleared to “0” at the end of the conversion.
(2) Scan mode: A/D conversion starts and continues cyclically on the selected
channels until the ADST bit is cleared to “0” by software (or a reset, or by entry to a
standby mode).
Bit 4Scan Mode (SCAN): This bit selects the scan mode or single mode of operation.
See section 11.3, “Operation” for descriptions of these modes.
The mode should be changed only when the ADST bit is cleared to “0.”
Bit 4
SCAN Description
0 Single mode (Initial value)
1 Scan mode