Hardware manual

Rev. 3.0, 09/98, page 230 of 361
11.2 Register Descriptions
11.2.1 A/D Data Registers (ADDR)H'FFE0 to H'FFE6
Bit:76543210
ADDRn:
Initial value:00000000
Read/Write: R R R R R R R R
(n = A to D)
The four A/D data registers (ADDRA to ADDRD) are 8-bit read-only registers that store the
results of A/D conversion. Each data register is assigned to two analog input channels as indicated
in table 11.3.
The A/D data registers are always readable by the CPU.
The A/D data registers are initialized to H'00 at a reset and in the standby modes.
Table 11.3 Assignment of Data Registers to Analog Input Channels
Analog Input Channel
Group 0 Group 1 A/D Data Register
AN0 AN4 ADDRA
AN1 AN5 ADDRB
AN2 AN6 ADDRC
AN3 AN7 ADDRD
11.2.2 A/D Control/Status Register (ADCSR)H'FFE8
Bit:76543210
ADF ADIE ADST SCAN CKS CH2 CH1 CH0
Initial value:00000000
Read/Write: R/(W)
*
R/W R/W R/W R/W R/W R/W R/W
Note: Software can write a “0” in bit 7 to clear the flag, but cannot write a “1” in this bit.
The A/D control/status register (ADCSR) is an 8-bit readable/writable register that controls the
operation of the A/D converter module.
The ADCSR is initialized to H'00 at a reset and in the standby modes.