Hardware manual

Rev. 3.0, 09/98, page 226 of 361
Basic clock
0123456789101112131415161234567891011121314151612345
–7.5 pulses
Start bit
+7.5 pulses
D0 D1
Receive data
Sync sampling
Data sampling
Figure 10.18 Sampling Timing (Asynchronous mode)
M = {(0.5 − 1/2N) − (D − 0.5)/N - (L − 0.5) F} × 100 [%] (1)
M: Receive margin
N: Ratio of basic clock to baud rate (N=16)
D: Duty factor of clock-ratio of High pulse width to Low width (0.5 to 1.0)
L: Frame length (9 to 12)
F: Absolute clock frequency deviation
When D = 0.5 and F = 0
M = (0.5 −1/2 × 16) × 100 [%] = 46.875% (2)