Hardware manual

Rev. 3.0, 09/98, page 225 of 361
Table 10.10 SSR Bit States and Data Transfer when Multiple Receive Errors Occur
SSR Bits
Receive Error RDRF ORER FER PER
RSR →
RDR
*
2
Overrun error 1*
1
100No
Framing error 0 0 1 0 Yes
Parity error 0 0 0 1 Yes
Overrun and framing errors 1*
1
110No
Overrun and parity errors 1*
1
101No
Framing and parity errors 0 0 1 1 Yes
Overrun, framing, and parity errors 1*
1
111No
Notes: 1. Set to “1” before the overrun error occurs.
2. Yes: The RSR contents are transferred to the RDR.
No: The RSR contents are not transferred to the RDR.
(3) Line Break Detection:
When the RxD pin receives a continuous stream of 0’s in
asynchronous mode (line-break state), a framing error occurs because the SCI detects a “0” stop
bit. The value H'00 is transferred from the RSR to the RDR. Software can detect the line-break
state as a framing error accompanied by H'00 data in the RDR.
The SCI continues to receive data, so if the FER bit is cleared to “0” another framing error will
occur.
(4) Sampling Timing and Receive Margin in Asynchronous Mode:
The serial clock used by
the SCI in asynchronous mode runs at 16 times the baud rate. The falling edge of the start bit is
detected by sampling the RxD input on the falling edge of this clock. After the start bit is
detected, each bit of receive data in the frame (including the start bit, parity bit, and stop bit or
bits) is sampled on the rising edge of the serial clock pulse at the center of the bit. See figure
10.18.
It follows that the receive margin can be calculated as in equation (1).
When the absolute frequency deviation of the clock signal is 0 and the clock duty factor is 0.5,
data can theoretically be received with distortion up to the margin given by equation (2). This is a
theoretical limit, however. In practice, system designers should allow a margin of 20% to 30%.