Hardware manual

Rev. 3.0, 09/98, page 222 of 361
After receiving the data, the SCI checks that RDRF is “0” so that receive data can be loaded
from RSR into RDR. If this check passes, the SCI sets RDRF to “1” and stores the received
data in RDR. If the check does not pass (receive error), the SCI operates as indicated in
table 10.8.
Note: Both transmitting and receiving are disabled while a receive error flag is set. The
RDRF bit is not set to “1.” Be sure to clear the error flag.
3. After setting RDRF to “1,” if the RIE bit (receive-end interrupt enable) is set to “1” in SCR,
the SCI requests an RXI (receive-end) interrupt. If the ORER bit is set to “1” and the RIE bit
in SCR is set to “1,” the SCI requests an ERI (receive-error) interrupt.
When clock output mode is selected, clock output stops when the RE bit is cleared to “0” or
the ORER bit is set to “1.” To prevent clock count errors, it is safest to receive one dummy
byte and generate an overrun error.
Figure 10.16 shows an example of SCI receive operation.
Serial
clock
Serial
data
Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
RXI
request
RDRF
ORER
RXI interrupt
handler reads
data in RDR and
clears RDRF to "0"
RXI
request
Overrun error,
ERI request
1 frame
Figure 10.16 Example of SCI Receive Operation
• Transmitting and Receiving Serial Data Simultaneously: Follow the procedure below for
transmitting and receiving serial data simultaneously. If clock output mode is selected, output
of the serial clock begins simultaneously with serial transmission.