Hardware manual

Rev. 3.0, 09/98, page 220 of 361
2. After loading the data from TDR into TSR, the SCI sets the TDRE bit to “1” and starts
transmitting. If the TIE bit (TDR-empty interrupt enable) in SCR is set to “1,” the SCI
requests a TXI interrupt (TDR-empty interrupt) at this time.
If clock output is selected the SCI outputs eight serial clock pulses, triggered by the clearing of
the TDRE bit to “0.” If an external clock source is selected, the SCI outputs data in
synchronization with the input clock.
Data are output from the TxD pin in order from LSB (bit 0) to MSB (bit 7).
3. The SCI checks the TDRE bit when it outputs the MSB (bit 7). If TDRE is “0,” the SCI loads
data from TDR into TSR, then begins serial transmission of the next frame. If TDRE is “1,”
the SCI sets the TEND bit in SSR to “1,” transmits the MSB, then holds the output in the MSB
state. If the TEIE bit (transmit-end interrupt enable) in SCR is set to “1,” a TEI interrupt
(TSR-empty interrupt) is requested at this time.
4. After the end of serial transmission, the SCK pin is held at the high level.
Figure 10.14 shows an example of SCI transmit operation.
Serial
clock
Serial
data
Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
TXI
request
TDRE
TEND
TXI interrupt
handler writes
data in TDR and
clears TDRE to "0"
TXI
request
TXI
request
1 frame
Figure 10.14 Example of SCI Transmit Operation
• Receiving Serial Data: Follow the procedure below for receiving serial data. When
switching from asynchronous mode to clocked synchronous mode, be sure to check that PER
and FER are cleared to “0.” If PER or FER is set to “1” the RDRF bit will not be set and both
transmitting and receiving will be disabled.