Hardware manual

Rev. 3.0, 09/98, page 208 of 361
Table 10.7 Data Formats in Asynchronous Mode
CHR
0
0
0
0
1
1
1
1
0
0
1
1
PE
0
0
1
1
0
0
1
1
—
—
—
—
MP
0
0
0
0
0
0
0
0
1
1
1
1
STOP
0
1
0
1
0
1
0
1
0
1
0
1
SMR Bits
123456789101112
S
S
S
S
S
S
S
S
S
S
S
S
8-Bit data
STOP
8-Bit data STOP STOP
8-Bit data
P
STOP
8-Bit data
P
STOP STOP
7-Bit data
STOP
7-Bit data
STOP
STOP
7-Bit data
P
STOP
7-Bit data
P
STOP STOP
8-Bit data
MPB STOP
8-Bit data
MPB
STOP STOP
7-Bit data MPB STOP
7-Bit data MPB STOP STOP
Notes: SMR: Serial mode register
S: Start bit
STOP: Stop bit
P: Parity bit
MPB: Multiprocessor bit
(2) Clock: In asynchronous mode it is possible to select either an internal clock created by the
on-chip baud rate generator, or an external clock input at the SCK pin. The selection is made by
the C/A bit in the serial mode register (SMR) and the CKE1 and CKE0 bits in the serial control
register (SCR). Refer to table 10.7.
If an external clock is input at the SCK pin, its frequency should be 16 times the desired bit rate.
If the internal clock provided by the on-chip baud rate generator is selected and the SCK pin is
used for clock output, the output clock frequency is equal to the bit rate, and the clock pulse rises
at the center of the transmit data bits. Figure 10.3 shows the phase relationship between the output
clock and transmit data.
“0” D0 D1 D2 D3 D4
One frame
D5 D6 D7 0/1 “1” “1”
Figure 10.3 Phase Relationship between Clock Output and Transmit Data
(Asynchronous Mode)