Hardware manual

Rev. 3.0, 09/98, page 200 of 361
10.2.8 Bit Rate Register (BRR)H'FFD9, H'FF89
Bit:76543210
Initial value:11111111
Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W
The BRR is an 8-bit register that, together with the CKS1 and CKS0 bits in the SMR, determines
the baud rate output by the baud rate generator.
The BRR is initialized to H'FF (the slowest rate) at a reset and in the standby modes.
Tables 10.3 and 10.4 show examples of BRR (N) and CKS (n) settings for commonly used bit
rates. Table 10.5 lists the maximum bit rates in asynchronous mode.
Table 10.3 Examples of BRR Settings in Asynchronous Mode (1)
XTAL Frequency (MHz)
2 2.4576 4 4.194304
Bit
Rate n N
Error
(%) n N
Error
(%) n N
Error
(%) n N
Error
(%)
110 1 70 +0.03 1 86 +0.31 1 141 +0.03 1 148 −0.04
150 0 207 +0.16 0 255 0 1 103 +0.16 1 108 +0.21
300 0 103 +0.16 0 127 0 0 207 +0.16 0 217 +0.21
600 0 51 +0.16 0 63 0 0 103 +0.16 0 108 +0.21
1200 0 25 +0.16 0 31 0 0 51 +0.16 0 54 −0.70
2400 0 12 +0.16 0 15 0 0 25 +0.16 0 26 +1.14
4800 070012+0.16013−2.48
9600 03006−2.48
19200 010
31250 0 0 0 010
38400 000