Hardware manual
Rev. 3.0, 09/98, page 198 of 361
Bit 4Framing Error (FER): This bit indicates a framing error during data reception in
asynchronous mode. It has no meaning in synchronous mode.
Bit 4
FER Description
0 To clear FER, the CPU must read FER after it has been set to “1,” (Initial value)
then write a “0” in this bit.
1 This bit is set to “1” if a framing error occurs (stop bit = “0”).
Bit 3Parity Error (PER): This bit indicates a parity error during data reception in the
asynchronous mode, when a communication format with parity bits is used.
This bit has no meaning in the synchronous mode, or when a communication format without
parity bits is used.
Bit 3
PER Description
0 To clear PER, the CPU must read PER after it has been set to “1,” (Initial value)
then write a “0” in this bit.
1 This bit is set to “1” when a parity error occurs (the parity of the received data does not
match the parity selected by the O/E bit in SMR).
Bit 2Transmit End (TEND): This bit indicates that the serial communication interface has
stopped transmitting because there was no valid data in the TDR when the last bit of the current
character was transmitted. The TEND bit is also set to “1” when the TE bit in the serial control
register (SCR) is cleared to “0.”
The TEND bit can be read but not written. To clear TEND to “0,” software must read the serial
status register while TDRE = “1,” then write “0” in TDRE.
Bit 2
TEND Description
0 To clear TEND, the CPU must read TDRE after it has been set to “1,” (Initial value)
then write a “0” in TDRE.
1 This bit is set to “1” when:
(1) TE = “0”
(2) TDRE = “1” at the end of transmission of a character