Hardware manual

Rev. 3.0, 09/98, page 197 of 361
10.2.7 Serial Status Register (SSR)H'FFDC, H'FF8C
Bit:76543210
TDRE RDRF ORER FER PER TEND MPB MPBT
Initial value:10000100
Read/Write: R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* RRR/W
Note: Software can write a “0” to clear the flags, but cannot write a “1” in these bits.
The SSR is an 8-bit register that indicates transmit and receive status. It is initialized to H'84 at a
reset and in the standby modes.
Bit 7Transmit Data Register Empty (TDRE):
This bit indicates when the TDR contents have
been transferred to the TSR and the next character can safely be written in the TDR.
Bit 7
TDRE Description
0 To clear TDRE, the CPU must read TDRE after it has been set to “1,”
then write a “0” in this bit.
1 This bit is set to 1 at the following times: (Initial value)
(1) When TDR contents are transferred to the TSR.
(2) When the TE bit in the SCR is cleared to “0.”
Bit 6Receive Data Register Full (RDRF):
This bit indicates when one character has been
received and transferred to the RDR.
Bit 6
RDRF Description
0 To clear RDRF, the CPU must read RDRF after it has been set to “1,” (Initial value)
then write a “0” in this bit.
1 This bit is set to 1 when one character is received without error and
transferred from the RSR to the RDR.
Bit 5Overrun Error (ORER):
This bit indicates an overrun error during reception.
Bit 5
ORER Description
0 To clear ORER, the CPU must read ORER after it has been set to “1,” (Initial value)
then write a “0” in this bit.
1 This bit is set to “1” if reception of the next character ends while
the receive data register is still full (RDRF = “1”).