Hardware manual
Rev. 3.0, 09/98, page 195 of 361
Bit 4Receive Enable (RE): This bit enables or disables the receive function. When the receive
function is enabled, the RxD pin is automatically used for input. When the receive function is
disabled, the RxD pin is available as a general-purpose I/O port.
Bit 4
RE Description
0 The receive function is disabled. The RxD pin can be (Initial value)
used for general-purpose I/O.
1 The receive function is enabled. The RxD pin is used for input.
Bit 3Multiprocessor Interrupt Enable (MPIE): When serial data are received in a
multiprocessor format, this bit enables or disables the receive-end interrupt (RxI) and receive-error
interrupt (ERI) until data with the multiprocessor bit set to “1” are received. It also enables or
disables the transfer of received data from the RSR to the RDR, and enables or disables setting of
the RDRF, FER, PER, and ORER bits in the serial status register (SSR).
The MPIE bit is ignored when the MP bit is cleared to “0,” and in synchronous mode.
Clearing the MPIE bit to “0” disables the multiprocessor receive interrupt function. In this
condition data are received regardless of the value of the multiprocessor bit in the receive data.
Setting the MPIE bit to “1” enables the multiprocessor receive interrupt function. In this
condition, if the multiprocessor bit in the receive data is “0,” the receive-end interrupt (RxI) and
receive-error interrupt (ERI) are disabled, the receive data are not transferred from the RSR to the
RDR, and the RDRF, FER, PER, and ORER bits in the serial status register (SSR) are not set. If
the multiprocessor bit is “1,” however, the MPB bit in the SSR is set to “1,” the MPIE bit is
cleared to “0,” the receive data are transferred from the RSR to the RDR, the FER, PER, and
ORER bits can be set, and the receive-end and receive-error interrupts are enabled.
Bit 3
MPIE Description
0 The multiprocessor receive interrupt function is disabled. (Initial value)
(Normal receive operation)
1 The multiprocessor receive interrupt function is enabled. During the interval before
data with the multiprocessor bit set to “1” are received, the receive interrupt request
(RxI) and receive-error interrupt request (ERI) are disabled, the RDRF, FER, PER, and
ORER bits are not set in the serial status register (SSR), and no data are transferred
from the RSR to the RDR. The MPIE bit is cleared at the following times:
(1) When “0” is written in MPIE.
(2) When data with the multiprocessor bit set to “1” are received.