Hardware manual

Rev. 3.0, 09/98, page 194 of 361
10.2.6 Serial Control Register (SCR)H'FFDA, H'FF8A
Bit:76543210
TIE RIE TE RE MPIE TEIE CKE1 CKE0
Initial value:00000000
Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W
The SCR is an 8-bit readable/writable register that enables or disables various SCI functions. It is
initialized to H'00 at a reset and in the standby modes.
Bit 7Transmit Interrupt Enable (TIE): This bit enables or disables the TDR-empty interrupt
(TxI) requested when the transmit data register empty (TDRE) bit in the serial status register
(SSR) is set to “1.”
Bit 7
TIE Description
0 The TDR-empty interrupt request (TxI) is disabled. (Initial value)
1 The TDR-empty interrupt request (TxI) is enabled.
Bit 6Receive Interrupt Enable (RIE): This bit enables or disables the receive-end interrupt
(RXI) requested when the receive data register full (RDRF) bit in the serial status register (SSR) is
set to “1,” and the receive error interrupt (ERI) requested when the overrun error (ORER), framing
error (FER), or parity error (PER) bit in the serial status register (SSR) is set to “1.”
Bit 6
RIE Description
0 The receive-end interrupt (RXI) and receive-error (ERI) requests are (Initial value)
disabled.
1 The receive-end interrupt (RXI) and receive-error (ERI) requests are enabled.
Bit 5Transmit Enable (TE): This bit enables or disables the transmit function. When the
transmit function is enabled, the TxD pin is automatically used for output. When the transmit
function is disabled, the TxD pin can be used as a general-purpose I/O port.
Bit 5
TE Description
0 The transmit function is disabled. (Initial value)
The TxD pin can be used for general-purpose I/O.
1 The transmit function is enabled. The TxD pin is used for output.