Hardware manual
Rev. 3.0, 09/98, page 191 of 361
10.2.4 Transmit Data Register (TDR)H'FFDB, H'FF8B
Bit:76543210
Initial value:11111111
Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W
The TDR is an 8-bit readable/writable register that holds the next character to be transmitted.
When the TSR becomes empty, the character written in the TDR is transferred to the TSR.
Continuous data transmission is possible by writing the next byte in the TDR while the current
byte is being transmitted from the TSR.
The TDR is initialized to H'FF at a reset and in the standby modes.
10.2.5 Serial Mode Register (SMR)H'FFD8, H'FF88
Bit:76543210
C/A CHR PE O/E STOP MP CKS1 CKS0
Initial value:10000000
Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W
The SMR is an 8-bit readable/writable register that controls the communication format and selects
the clock rate for the internal clock source. It is initialized to H'00 at a reset and in the standby
modes. For further information on the SMR settings and communication formats, see tables 10.5
and 10.7 in section 10.3, “Operation.”
Bit 7Communication Mode (C/A): This bit selects the asynchronous or clocked synchronous
communication mode.
Bit 7
C/A Description
0 Asynchronous communication. (Initial value)
1 Clocked synchronous communication.