Hardware manual

Rev. 3.0, 09/98, page 186 of 361
iii) If the DTR value is changed (by writing the data “M” in figure 9.3), the new value
becomes valid after the timer count changes from H'F9 to H'00. [(d) in figure 9.3]
(2) Negative Logic (OS = “1”) - (e) in Figure 9.3: The operation is the same except that High
and Low are reversed in the PWM output. [(e) in figure 9.3]
9.4 Application Notes
Some notes on the use of the PWM timer module are given below.
(1) Any necessary changes to the clock select bits (CKS2 to CKS0) and output select bit (OS)
should be made before the output enable bit (OE) is set to “1.”
(2) If the DTR value is H'00, the duty cycle is 0% and PWM output remains constant at “0.”
If the DTR value is H'FA to H'FF, the duty cycle is 100% and PWM output remains constant at
“1.”
(For positive logic, “0” is Low and “1” is High. For negative logic, “0” is High and “1” is
Low.)