Hardware manual

Rev. 3.0, 09/98, page 182 of 361
9.2.2 Duty Register (DTR)H'FFA1 (PWM0), H'FFA5 (PWM1)
Bit:76543210
Initial value:11111111
Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W
The duty registers (DTR) are 8-bit readable/writable registers that specify the duty cycle of the
output pulse. Any duty cycle from 0 to 100% can be selected, with a resolution of 1/250. Writing
0 (H'00) in a DTR gives a 0% duty cycle; writing 125 (H'7D) gives a 50% duty cycle; writing 250
(H'FA) gives a 100% duty cycle.
The timer count is continually compared with the DTR contents. If the DTR value is not 0, when
the count increments from H'00 to H'01 the PWM output signal is set to “1.” When the count
increments past the DTR value, the PWM output returns to “0.” If the DTR value is 0 (0% duty),
the PWM output remains constant at “0.”
The DTRs are double-buffered. A new value written in a DTR while the timer counter is running
does not become valid until after the count changes from H'F9 to H'00. When the timer counter is
stopped (while the OE bit is “0”), new values become valid as soon as written. When a DTR is
read, the value read is the currently valid value.
The DTRs are initialized to H'FF at a reset and in the standby modes.
9.2.3 Timer Control Register (TCR)H'FFA0 (PWM0), H'FFA4 (PWM1)
Bit:76543210
OE OS CKS2 CKS1 CKS0
Initial value:00111000
Read/Write: R/W R/W R/W R/W R/W
The TCRs are 8-bit readable/writable registers that select the clock source and control the PWM
outputs.
The TCRs are initialized to H'38 at a reset and in the standby modes.