Hardware manual

Rev. 3.0, 09/98, page 180 of 361

9.1.2 Block Diagram

Figure 9.1 shows a block diagram of one PWM timer channel.

Pulse

DTR

Output

control

Comparator

TCNT

TCR

Internal

data bus

Internal clock sources

Clock

select

Compare-match

DTR

TCNT

TCR

Legend:

: Timer Control Register (8 bits)

: Duty Register (8 bits)

: Times Counter (8 bits)

Ø/2

Ø/8

Ø/32

Ø/128

Ø/256

Ø/1024

Ø/2048

Ø/4096

Module data bus

Bus interface

Figure 9.1 Block Diagram of PWM Timer