Hardware manual

Rev. 3.0, 09/98, page 176 of 361
(3) Contention between TCOR Write and Compare-Match: If a compare-match occurs
during the T
3
state of a write cycle to TCORA or TCORB, the write takes precedence and the
compare-match signal is inhibited.
Figure 8.12 shows this type of contention.
Ø
Internal address
bus
Internal write
signal
TCNT
TCORA or
TCORB
Compare-match
A or B signal
Write cycle: CPU writes to TCORA or TCORB
T
1 T2 T3
N + 1
N
TCOR write data
Inhibited
NM
TCOR address
Figure 8.12 Contention between TCOR Write and Compare-Match
(4) Contention between Compare-Match A and Compare-Match B: If identical time
constants are written in TCORA and TCORB, causing compare-match A and B to occur
simultaneously, any conflict between the output selections for compare-match A and B is resolved
by following the priority order in table 8.4.
Table 8.4 Priority of Timer Output
Output Selection Priority
Toggle High
“1” Output
“0” Output
No change Low