Hardware manual

Rev. 3.0, 09/98, page 175 of 361
(2) Contention between TCNT Write and Increment: If a timer counter increment pulse is
generated during the T
3
state of a write cycle to the timer counter, the write takes priority and the
timer counter is not incremented.
Figure 8.11 shows this type of contention.
Ø
Internal Address
bus
Internal write
signal
TCNT clock pulse
TCNT
Write cycle: CPU writes to TCNT
T
1 T 2 T 3
Write data
NM
TCNT address
Figure 8.11 TCNT Write-Increment Contention