Hardware manual

Rev. 3.0, 09/98, page 174 of 361
8.6 Application Notes
Application programmers should note that the following types of contention can occur in the 8-bit
timer.
(1) Contention between TCNT Write and Clear: If an internal counter clear signal is generated
during the T
3
state of a write cycle to the timer counter, the clear signal takes priority and the write
is not performed.
Figure 8.10 shows this type of contention.
Ø
Internal Address
bus
Internal write
signal
Counter clear
signal
TCNT
Write cycle: CPU writes to TCNT
T
1 T2 T3
H' 00
N
TCNT address
Figure 8.10 TCNT Write-Clear Contention