Hardware manual

Rev. 3.0, 09/98, page 172 of 361
8.3.3 External Reset of TCNT
When the CCLR1 and CCLR0 bits in the TCR are both set to “1,” the timer counter is cleared on
the rising edge of an external reset input. Figure 8.7 shows the timing of this operation. The timer
reset pulse width must be at least 1.5 system clock periods.
N
N - 1
N' 00
External reset
input (TMRI)
Internal clear
pulse
Ø
TCNT
Figure 8.7 Timing of External Reset
8.3.4 Setting of TCSR Overflow Flag (OVF)
The overflow flag (OVF) is set to “1” when the timer count overflows (changes from H'FF to
H'00). Figure 8.8 shows the timing of this operation.
H' FF H' 00
TCNT
Ø
Internal overflow
signal
OVF
Figure 8.8 Setting of Overflow Flag (OVF)