Hardware manual

Rev. 3.0, 09/98, page 171 of 361
(2) Output Timing: When a compare-match event occurs, the timer output (TMO0 or TMO1)
changes as specified by the output select bits (OS3 to OS0) in the TCSR. Depending on these bits,
the output can remain the same, change to “0,” change to “1,” or toggle.
Figure 8.5 shows the timing when the output is set to toggle on compare-match A.
Internal
compare-match
A signal
Timer output
(TMO)
Ø
Figure 8.5 Timing of Timer Output
(3) Timing of Compare-Match Clear: Depending on the CCLR1 and CCLR0 bits in the TCR,
the timer counter can be cleared when compare-match A or B occurs. Figure 8.6 shows the timing
of this operation.
N
N' 00
Internal
compare-match
signal
TCNT
Ø
Figure 8.6 Timing of Compare-Match Clear