Hardware manual

Rev. 3.0, 09/98, page 166 of 361
8.2.4 Timer Control/Status Register (TCSR)H'FFC9 (TMR0), H'FFD1 (TMR1)
Bit:76543210
CMFB CMFA OVF  OS3 OS2 OS1 OS0
Initial value:00010000
Read/Write: R/(W)* R/(W)* R/(W)*  R/W R/W R/W R/W
Note: Software can write a “0” in bits 7 to 5 to clear the flags, but cannot write a “1” in these bits.
The TCSR is an 8-bit readable and partially writable register that indicates compare-match and
overflow status and selects the effect of compare-match events on the timer output signal.
The TCSR is initialized to H'10 at a reset and in the standby modes.
Bit 7Compare-Match Flag B (CMFB):
This status flag is set to “1” when the timer count
matches the time constant set in TCORB. CMFB must be cleared by software. It is set by
hardware, however, and cannot be set by software.
Bit 7
CMFB Description
0 To clear CMFB, the CPU must read CMFB after it has been set to “1,” (Initial value)
then write a “0” in this bit.
1 This bit is set to 1 when TCNT = TCORB.
Bit 6Compare-Match Flag A (CMFA):
This status flag is set to “1” when the timer count
matches the time constant set in TCORA. CMFA must be cleared by software. It is set by
hardware, however, and cannot be set by software.
Bit 6
CMFA Description
0 To clear CMFA, the CPU must read CMFA after it has been set to “1,” (Initial value)
then write a “0” in this bit.
1 This bit is set to 1 when TCNT = TCORA.