Hardware manual

Rev. 3.0, 09/98, page 164 of 361
Bit 5Timer Overflow Interrupt Enable (OVIE): This bit selects whether to request a timer
overflow interrupt (OVI) when the overflow flag (OVF) in the timer control/status register
(TCSR) is set to “1.”
Bit 5
OVIE Description
0 The timer overflow interrupt request (OVI) is disabled. (Initial value)
1 The timer overflow interrupt request (OVI) is enabled.
Bits 4 and 3Counter Clear 1 and 0 (CCLR1 and CCLR0): These bits select how the timer
counter is cleared: by compare-match A or B or by an external reset input.
Bit 4
CCLR1
Bit 3
CCLR0 Description
0 0 Not cleared. (Initial value)
0 1 Cleared on compare-match A.
1 0 Cleared on compare-match B.
1 1 Cleared on rising edge of external reset input signal.