Hardware manual

Rev. 3.0, 09/98, page 163 of 361
Compare-match is not detected during the T
3
state of a write cycle to TCORA or TCORB. See
item (3) in section 8.6, “Application Notes.”
8.2.3 Timer Control Register (TCR)H'FFC8 (TMR0), H'FFD0 (TMR1)
Bit:76543210
CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0
Initial value:00000000
Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W
Each TCR is an 8-bit readable/writable register that selects the clock source and the time at which
the timer counter is cleared, and enables interrupts.
The TCRs are initialized to H'00 at a reset and in the standby modes.
For timing diagrams, see section 8.3, “Operation.”
Bit 7Compare-match Interrupt Enable B (CMIEB): This bit selects whether to request
compare-match interrupt B (CMIB) when compare-match flag B (CMFB) in the timer
control/status register (TCSR) is set to “1.”
Bit 7
CMIEB Description
0 Compare-match interrupt request B (CMIB) is disabled. (Initial value)
1 Compare-match interrupt request B (CMIB) is enabled.
Bit 6Compare-match Interrupt Enable A (CMIEA): This bit selects whether to request
compare-match interrupt A (CMIA) when compare-match flag A (CMFA) in the timer
control/status register (TCSR) is set to “1.”
Bit 6
CMIEA Description
0 Compare-match interrupt request A (CMIA) is disabled. (Initial value)
1 Compare-match interrupt request A (CMIA) is enabled.