Hardware manual

Rev. 3.0, 09/98, page 157 of 361
Table 7.5 Effect of Changing Internal Clock Sources (cont)
No. Description Timing chart
3 High → Low:
CKS1 and CKS0 are
rewritten while old
clock source is High and
new clock source is Low.
Old clock
source
New clock
source
FRC clock
pulse
FRC N N + 1 N + 2
CKS rewrite
*
4 High → High:
CKS1 and CKS0 are
rewritten while both
clock sources are High.
Old clock
source
New clock
source
FRC clock
pulse
FRC
N N + 1
CKS rewrite
N + 2
Note: The switching of clock sources is regarded as a falling edge that increments the FRC.