Hardware manual

Rev. 3.0, 09/98, page 155 of 361
Figure 7.18 shows this type of contention.
Ø
Internal address bus
Internal write signal
FRC
OCRA or OCRB
Compare-match
A or B signal
Write cycle: CPU write to lower byte of OCRA or OCRB
T
1 T2 T3
N + 1
N
M
Inhibited
N
OCR address
Write data
Figure 7.18 FRC Write-Increment Contention
(3) Contention between OCR Write and Compare-Match: If a compare-match occurs during
the T
3
state of a write cycle to the lower byte of OCRA or OCRB, the write takes priority and the
compare-match signal is inhibited.