Hardware manual

Rev. 3.0, 09/98, page 154 of 361
7.7 Application Notes
Application programmers should note that the following types of contention can occur in the free-
running timers.
(1) Contention between FRC Write and Clear: If an internal counter clear signal is generated
during the T
3
state of a write cycle to the lower byte of the free-running counter, the clear signal
takes priority and the write is not performed.
Figure 7.17 shows this type of contention.
Ø
Internal address bus
Internal write signal
FRC clock pulse
FRC
Write cycle: CPU write to lower byte of FRC
T
1 T 2 T 3
Write data
NM
FRC address
Figure 7.17 FRC Write-Clear Contention
(2) Contention between FRC Write and Increment: If an FRC increment pulse is generated
during the T
3
state of a write cycle to the lower byte of the free-running counter, the write takes
priority and the FRC is not incremented.