Hardware manual

Rev. 3.0, 09/98, page 151 of 361

Figure 7.13 shows how input capture operates when ICRA and ICRC are used in buffer mode and

IEDGA and IEDGC are set to different values (IEDGA = 0 and IEDGC = 1, or IEDGA = 1 and

IEDGC = 0), so that input capture is performed on both the rising and falling edges of FTIA.

N + 1

FRC

OCRA or B

Internal compare-

match signal

OCFA or B

Figure 7.13 Buffered Input Capture with Both Edges Selected

In this mode, input capture does not cause the FRC contents to be copied to ICRC. However,

input capture flag C still sets on the input capture edge selected by IEDGC, and if the interrupt

enable bit (ICICE) is set, a CPU interrupt is requested.

The situation when ICRB and ICRD are used in buffer mode is similar.

(2) Timing of Input Capture Flag (ICF) Setting: The input capture flag ICFx (x = A, B, C, D)

is set to “1” by the internal input capture signal. Figure 7.14 shows the timing of this operation.

H' 0000

Internal compare-

match A signal

FRC

Figure 7.14 Setting of Input Capture Flag